Introduction

High-quality, low-defect SiC substrates serve as the foundation for manufacturing high-performance power devices, yet they are not the final determining factor of device quality. Unlike mature silicon-based semiconductor processes, silicon carbide features extremely stable chemical bonds, bringing unique technical challenges to subsequent manufacturing procedures including doping, annealing, etching, thermal oxidation, and metal contact formation.
The superposition of native substrate defect propagation and newly introduced process defects, together with inherent physical mechanism limitations, jointly restrict the production yield and long-term reliability of SiC devices. Based on authoritative experimental data from academic papers, this article comprehensively analyzes the core challenges of SiC substrate-derived processes and the industrial iteration roadmap from four dimensions: key backend process pain points, defect generation mechanisms, defect impacts on device performance, and the full industrial technical and product development layout.

1. Core Backend Process Barriers: High-Temperature Ion Implantation and Dopant Activation

Silicon semiconductors realize efficient doping through impurity diffusion. However, the diffusion effect of impurities in SiC is almost negligible. All n-type and p-type active regions as well as junction termination structures of SiC devices can only be formed via ion implantation. This fundamental difference marks the biggest technical gap between SiC and silicon manufacturing processes and constitutes the primary bottleneck in SiC device fabrication.

1.1 Requirements for High-Temperature Ion Implantation

SiC possesses extremely high chemical bond energy. Room-temperature high-dose ion implantation continuously bombards the crystal lattice, causing irreversible lattice amorphization and cumulative defects, which directly damage the structural integrity of substrates and epitaxial layers. To reduce defect density, the industry universally adopts high-temperature ion implantation at approximately 500°C. The high-temperature environment activates lattice migration, suppresses bombardment-induced damage, and effectively minimizes defect accumulation.

1.2 Challenges of Ultra-High-Temperature Annealing Activation

After ion implantation, most dopant impurities reside in interstitial lattice positions without electrical activity and cannot conduct current. Ultra-high-temperature annealing is mandatory to achieve substitutional dopant activation and repair lattice damage. The activation temperature required for SiC doping is far higher than that for silicon, with distinct differences between doping types:

• N-type doping (Nitrogen, N): Relatively easy to activate, achieving an activation rate of 10%–20% at 1400°C;

• P-type doping (Aluminum, Al): Extremely difficult to activate. Under identical doping concentrations, the required annealing temperature is 100–300°C higher than that for n-type doping. The activation rate of conventional processes is merely 10%–20%, and high-concentration doping requires ultra-high-temperature annealing above 1800°C.

 

【Figure 1: Curve Diagram of the Relationship Between Annealing Temperature, Dopant Activation Rate and Substrate Resistivity】
 

1.3 Core Difficulties in Surface Protection During Annealing

Under ultra-high-temperature annealing environments above 1600°C, silicon atoms on the SiC substrate surface are highly prone to volatilization and loss, resulting in surface roughening and lattice degradation, which severely damage the quality of substrates and epitaxial layers. The industry has developed multiple mature protection solutions, including graphite carbon capping, single-layer AlN protection, BN/AlN composite protection, and silane overpressure atmosphere annealing. Among them, the graphite carbon capping process has become the mainstream industrial solution due to its low cost, excellent stability and easy removal characteristics.

1.4 Key Physical Limitation: Incomplete Ionization of P-Type Doping

Aluminum (Al), the core p-type acceptor dopant for SiC, features an ionization energy exceeding 200meV, far higher than conventional dopants used in silicon processes. At room temperature, most substitutionally activated Al impurities cannot be ionized and fail to contribute hole carriers.
This inherent physical characteristic creates a technical trade-off: achieving the target high hole concentration requires a significant increase in ion implantation dosage, while high-dose implantation inevitably introduces massive new lattice defects. This incomplete ionization effect cannot be completely eliminated and represents the core physical bottleneck of SiC p-type processes.
It directly affects the design accuracy of JTE (Junction Termination Extension) structures and device bulk regions. Simulation and design must incorporate additional ionization rate correction parameters, instead of directly calculating carrier concentration based on doping density.

【Figure 2: Theoretical Curve of Acceptor Incomplete Ionization Rate Under Different Temperatures and Doping Concentrations】

2. Chain Reaction of Substrate Defects: Defect Propagation and Generation Throughout the Process Chain

The vast majority of SiC device failures can be traced back to the chain propagation of substrate defects. Native substrate defects, including micropipes, screw dislocations, basal plane dislocations and stacking faults, are completely replicated in the epitaxial layer. Meanwhile, new defects are continuously generated during backend manufacturing processes, jointly deteriorating overall device performance:

• Carbon-based interface defects: During thermal oxidation, decomposed carbon elements form carbon interstitials, carbon dimers, carbon dangling bonds and other defects at the SiC/SiO₂ interface, constituting the primary source of Near-Interface Traps (NITs);

• Etching-induced defects: Dry etching easily triggers micro-trenches, sidewall undercutting and micro-masking effects, distorting device morphology, causing electric field concentration, and reducing device breakdown voltage;

• Residual annealing defects: Lattice damage and compensation centers remaining after ultra-high-temperature annealing increase device on-resistance and reduce carrier mobility.

For automotive-grade and aerospace-grade SiC devices, substrate micropipe density and dislocation density are mandatory access indicators. Even minor substrate defects may lead to dynamic failure and reliability degradation of devices during long-term operating conditions.

3. Decisive Influence of Substrate Quality on Core Backend Processes

3.1 Impact on Thermal Oxidation Gate Dielectric Processes

The SiO₂ gate dielectric formed by SiC thermal oxidation naturally contains high-density interface traps, and native defects in substrates and epitaxial layers further amplify trap density. High-concentration interface traps scatter channel carriers, significantly reducing MOSFET channel mobility and increasing on-resistance. Meanwhile, they interfere with the electric field distribution of JTE junction termination structures, weaken device voltage resistance stability, and restrict the reliability of high-voltage devices. Substrates with lower defect density can maximize the optimization effect of subsequent NO and N₂O passivation processes.

3.2 Impact on Ohmic Contact Processes

The ohmic contact resistance of source, drain and back electrodes of SiC devices directly determines device conduction loss and thermal stability. The surface flatness, cleanliness and defect density of substrates fundamentally determine the interface quality between metal and semiconductor. Substrates with high defect density result in uneven contact resistance and poor thermal stability, easily causing contact degradation and device failure under long-term high-temperature operating conditions.

4. Full Industrial Technical and Product Roadmap for SiC Substrates and Devices

Combined with industrial iteration trends and academic research findings, the SiC industry has formed a clear three-level upgrading roadmap, with all core iterations centered on substrate technology optimization:

4.1 Substrate Layer Iteration

Size upgrading: Popularization of mature 150mm mass production → large-scale industrialization of 200mm ultra-large-size wafers; Quality upgrading: Continuous reduction of micropipe, dislocation and stacking fault density to meet stringent reliability standards for automotive and aerospace applications; Cost optimization: Optimization of PVT crystal growth processes and large-scale adoption of Smart-Cut composite substrate technology to improve material utilization, boost production yield and achieve cost reduction and efficiency improvement.

4.2 Process Layer Iteration

Optimize high-temperature ion implantation and ultra-high-temperature annealing processes to reduce doping defects and improve dopant activation rate; upgrade dry etching technology to eliminate morphological defects such as micro-trenches and micro-masking; optimize thermal oxidation and interface passivation processes to drastically reduce interface trap density; develop high-stability, low-resistance ohmic contact processes suitable for long-term high-temperature and high-voltage operation; upgrade high-reliability power packaging technologies to match the high-frequency and high-temperature characteristics of SiC devices.

4.3 Device Product Layer Iteration

Fully cover mainstream power scenarios with voltage grades ranging from 650V to 1700V; upgrade device architecture from traditional planar MOSFETs to trench MOSFETs to continuously reduce specific on-resistance; expand application coverage to high-end fields including new energy vehicles, photovoltaic energy storage, industrial transmission, rail transit and aerospace.

5. Industrial Summary

Essentially, all process difficulties and performance bottlenecks of SiC devices stem from the intrinsic material characteristics and manufacturing limitations of SiC substrates. As the physical carrier of devices and the core origin of industrial technological iteration, substrates have redefined industrial competition boundaries. Current SiC industry competition has gone beyond device design and packaging, evolving into comprehensive competition covering substrate quality control, defect engineering and full-process collaborative optimization.
With continuous breakthroughs in large-size low-defect substrate technology and innovative composite substrate solutions, SiC devices will completely resolve cost and reliability pain points, fully replace traditional silicon-based power devices, and become a core support for global energy transformation and industrial upgrading.
JXT specializes in the supply of silicon carbide substrates, stably providing full-series 2–12 inch SiC substrate products. We meet both R&D sample trial and large-scale mass production requirements, delivering products with excellent consistency and reliability that fully adapt to various SiC power device manufacturing processes and high-end application scenarios.