Introduction

For substrate suppliers, a bonded substrate is not merely "visually compliant, void-free, and mechanically robust" — what matters far more is its electrical performance. As we observed in the preceding article: two nominally identical 100 mm Si-on-SiC bonded substrates, both starting with n-type silicon device layers, exhibit p-type electrical response at 2 μm thickness, and only approach n-type characteristics when thinned to 1 μm.
The doping has not changed. The root cause lies in the bonded heterojunction interface and the thin-film damage introduced during substrate processing. This article, supported by TCAD simulation, dissects the interfacial risks inherent to bonded substrates, key specification selection criteria, and practical guidance for customer applications.
 

1. Experimental Observations: A Recap

Test samples: Si-on-SiC bonded substrates fabricated on semi-insulating 4H-SiC handle wafers, with silicon device layers of two thickness specifications — 1 μm and 2 μm. Lateral MOS capacitors (LMOS-Cs) were fabricated on the substrates to evaluate electrical quality.

• 2 μm silicon device layer: C-V curves exhibit clear p-type characteristics.

• 1 μm silicon device layer: Electrical behavior approaches n-type, yet residual frequency dispersion and incomplete charge accumulation persist.

• Bulk silicon reference: Conventional bulk silicon wafers show none of these anomalies, confirming that the effects originate from the heterogeneous Si/SiC bonded structure.

Three candidate sources of the anomalies:

1. Interfacial trap charges at the Si/SiC bonded interface (bottom interface).

2. MOS oxide interface traps at the top surface of the silicon device layer.

3. Thin-film damage layers within the silicon device layer, introduced by bonding, grinding, and etching processes.

 

2. Decoding the Electrical Effects Within the Bonded Substrate

A two-dimensional TCAD model was built to replicate the BP2-process Si-on-SiC substrate structure. Different interfacial trap densities were introduced sequentially to simulate the substrate's electrical response.

2.1 Scenario 1: Interfacial Trap Charges Only (Both Interfaces)

Parameter setup:

• Si/SiC bottom bonded interface trap density: N = 1 × 10¹³ cm⁻²

• Top MOS interface trap density: N = 6 × 10¹⁰ cm⁻²

Simulation result: This configuration successfully reproduces the frequency dispersion observed in the 1 μm-thick Si-on-SiC substrate.

However, interfacial charges alone cannot explain the complete p-type inversion observed in the 2 μm-thick device layer. With a thicker silicon film, interface charges alone are insufficient to fully deplete the entire silicon layer.

2.2 Scenario 2: Adding Process-Induced Damage Layer Within the Silicon Film

Model assumptions:

• A 300 nm process-induced damage region exists within the silicon device layer, inherited from the original SOI BOX interface.

• Carrier lifetime in the damaged region is reduced to 1 ps.

• Acceptor-like bulk trap density introduced: N = 1 × 10¹⁶ cm⁻³.

• Top MOS interface trap density increased to: N = 6 × 10¹³ cm⁻².

With the damage layer incorporated, the simulation fully reproduces the complete p-type inversion C-V curves measured on the 2 μm substrate.
 

 
[Figure 1: Comparison of simulated C-V curves versus experimental measurement results for Si-on-SiC LMOS-Cs]
 

3. Core Physical Concepts

3.1 Thin-Film Pinching Effect

In Si-on-SiC bonded substrates, trap charges at both interfaces — the bottom Si/SiC bonded interface and the top silicon surface — extend depletion regions inward from both sides. The thinner the silicon film, the more readily the conductive channel is compressed, raising the equivalent series resistance of the substrate and giving rise to electrical frequency dispersion. This phenomenon is also well-documented in SOS (silicon-on-sapphire) bonded substrate systems.

Substrate physics interpretation: High-density interfacial trap charges at the Si/SiC bonded interface form a depletion region extending upward from the substrate bottom. When the silicon film is very thin, this depletion region pinches off the conductive channel, increasing the equivalent series resistance and causing C-V frequency dispersion. This is an intrinsic interfacial effect inherent to heterogeneous bonded substrates, and is directly correlated with SiC substrate quality and the bonding process.

3.2 "n-type substrate, p-type measurement" — An Electrical Artifact, Not Doping Error

Important: The silicon device layer remains n-type doped — the substrate material has not undergone doping inversion to p-type. Instead, it is the combined coupling of bonded-interface traps, process-induced traps within the silicon film, trap charge/discharge dynamics, and carrier recombination that produces the measured p-type C-V response.

 

Substrate business insight: The 2 μm device layer retains the damage layer inherited from the original SOI BOX interface. The 1 μm device layer, through dry-etch thinning, removes this damage layer — yielding significantly improved electrical behavior. This explains why the same bonding process can produce substrates with vastly different electrical performance depending on device-layer thickness.

 

4. Practical Implications for Substrate Suppliers and Customer Specification Selection

4.1 The Bonded Interface Is the Critical Quality Control Point

QC is not limited to visual inspection for voids or measurement of bond strength. The uniformity of the interfacial oxide layer at the Si/SiC bonded interface and its interfacial trap density directly determine the electrical quality of the entire substrate. Even when low-temperature bonding achieves a 97% yield, interfacial charges remain the key bottleneck and the primary focus for substrate iteration and optimization.

4.2 Device-Layer Thickness Is a Core Specification Parameter

• The 2 μm device layer offers higher voltage-withstanding potential, but readily carries residual SOI interface damage and suffers from poor electrical uniformity.

• The 1 μm device layer delivers superior electrical quality, but at the expense of lower breakdown voltage.

When recommending solutions to customers, this trade-off must be communicated transparently.

Specification selection note: Customers selecting 2 μm device-layer Si-on-SiC substrates must accept the associated risk of electrical anomalies. The 1 μm device layer avoids the inherited damage layer, but with reduced voltage capability — customers must weigh breakdown voltage against electrical quality.

4.3 Electrical Characterization Is Mandatory, Not Just Visual Inspection

Evaluating Si-on-SiC bonded substrates cannot rely on appearance inspection alone. C-V and complementary electrical characterization must be performed to assess interfacial trap levels — otherwise downstream devices will suffer from leakage current, elevated series resistance, and performance drift.

5. Summary

Si-on-SiC bonded substrates, built on semi-insulating 4H-SiC handle wafers with a thin silicon film transferred via wafer bonding, represent a distinctive heterogeneous platform for aerospace and extreme-environment applications.
The performance bottleneck of these substrates does not stem primarily from the SiC handle itself, but rather from: (1) interfacial traps at the Si/SiC bonded interface, and (2) process-induced damage within the silicon device layer.
In substrate sales and customer engagement, beyond providing hardware parameters such as dimensions, resistivity, device-layer thickness, and bonding yield, it is equally important to communicate the electrical risks introduced by interfacial charges — enabling customers to make informed substrate specification selections.
 

 

About JXT JXT specializes in the supply of diverse semiconductor substrate wafers, including high-quality silicon polished wafers, semi-insulating and conductive 4H-SiC substrates. We also provide custom wafer-bonding services tailored to customer requirements, covering a wide range of heterogeneous and homogeneous bonding configurations — including Si/SiC, Si/SiO₂, and SiC/SiC — with wafer sizes ranging from 2-inch to 8-inch.